The Optimal and Fail-Safe default settings are.
The settings are: Setting Description Disabled amibios test all system memory.
Turbo Switch Set this option to Enabled to permit amibios to control the hardware turbo (speed) switch.
Slow Clock Ratio This option specifies the speed at which the system clock runs in power saving modes.The available IRQ pool is determined by reading the escd nvram.You must then enter the drive parameters on the screen that appears.Fail-Safe bios Setup Settings You can load the Fail-Safe winbios Setup option settings by selecting the Fail-Safe icon from the Default section of the winbios Setup main menu.SectorsNumber of Sectors The number of sectors per track.Parallel Port DMA This option is only available if the setting for the Parallel Port Mode option is ECP.Amibios Password Support The Supervisor and User icons activate two different levels of password security.PCI/PnP Setup, configure PCI and Plug-and-Play features.PCI Latency Timer (in PCI Clocks) This option sets latency of all PCI devices on the PCI bus.
This is the default setting.
Hard Disk Timeout (Min) This option specifies the length of a period of hard disk inactivity.The settings are: Setting Description Disabled Neither L1 internal cache memory on the CPU or L2 secondary cache memory is enabled.Write PrecompensationWrite Precompensation The size of a sector gets progressively smaller as the track diameter diminishes.Landing ZoneLanding Zone This number is the cylinder location where the heads will normally zoombinis logical journey mac os x park when the system is shut down.Each window corresponds to a section below, with each window and each section containing several icons.The settings are Disabled, DMA CH (channel) 0, DMA CH 1, or DMA.How to correctly setup the bios and why you shold enable or disable certain settings.Typematic Rate This option specifies the speed at which a keyboard keystroke is repeated.System bios Shadow Cacheable When this option is set to Enabled, the contents of the F0000h system memory segment can be read from or written to L2 secondary cache memory.